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1 ? caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners. cmos asynchronous the 82C50a asynchronous communication element (ace) is a high performanc e programmable universal asynchronous receiver/transmitter (uart) and baud rate generator (brg) on a single chip. using intersil?s advanced scaled saji iv cmos process, the ace will support data rates from dc to 625k baud (0-10mhz clock). the ace?s receiver circuitry converts start, data, stop, and parity bits into a parallel data word. the transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. the word length is programmable to 5, 6, 7, or 8 data bits. stop bit selection provides a choice of 1,1.5, or 2 stop bits. the baud rate generator divides the clock by a divisor programmable from 1 to 2 16 -1 to provide standard rs- 232c baud rates when using any one of three industry standard baud rate crystals (1.8432mhz, 2.4576mhz, or 3.072mhz). a programmable buffered clock output (baudout) provides either a buffered oscillator or 16x (16 times the data rate) baud rate clock for general purpose system use. to meet the system requirements of a cpu interfacing to an asynchronous channel, the modem control signals rts , cts , dsr , dtr , ri , dcd are provided. inputs and outputs have been designed with full ttl/cmos compatibility in order to facilitate mixed ttl /nmos/cmos system design. features ? single chip uart/brg ? dc to 625k baud (dc to 10mhz clock) ? crystal or external clock input ? on chip baud rate generator 1 to 65535 divisor generates 16x clock ? prioritized interrupt mode ? fully ttl/cmos compatible ? microprocessor bus oriented interface ? 80c86/80c88 compatible ? scaled saji iv cmos process ? low power - 1ma/mhz typical ? modem interface ? line break generation and detection ? loopback and echo modes ? doubled buffered transmitter and receiver ? single 5v supply functional diagram ordering information package temperature range ( o c) 625k baud pkg. dwg. # pdip 0 to +70 cp82C50a-5 e40.6 plcc 0 to +70 cs82C50a-596 n44.65 -40 to +85 is82C50a-5 n44.65 d0 d1 d2 d3 d4 d5 d6 d7 1 2 3 4 5 6 7 8 a0 a1 a2 mr distr distr dostr dostr 28 27 26 35 22 21 19 18 cso cs1 cs2 12 13 14 ads 25 microprocessor interface interrupt enable, id, & control 30 intrpt 23 ddis 24 csout 10 sin uart modem divisor latch and baud rate generator modem control modem status receiver transmitter 9 rclk 16 xtal1 15 baudout 17 xtal2 11 sout 32 rts 33 dtr 34 out1 31 out2 36 cts 37 dsr 38 dcd 39 ri line status and control fn2958.2 82C50a data sheet may 2003
2 82C50a pinout 82C50a (pdip) top view 82C50a (plcc) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 d0 d1 d2 d3 d4 d5 d6 d7 rclk sin sout cs0 cs1 cs2 baudout xtal1 xtal2 dostr dostr gnd 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v cc ri dcd dsr cts mr out1 dtr rts out2 intrpt nc a0 a1 a2 ads csout ddis distr distr 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 20 21 22 23 24 25 26 19 18 7 8 9 10 11 12 13 14 15 16 17 d5 d6 d7 rclk sin nc sout cs0 cs1 cs2 baudout d4 d3 d2 d1 d0 nc v cc ri dcd dsr cts xtal1 xtal2 dostr dostr gnd nc distr distr ddis csout ads mr out1 dtr rts out2 nc intrp nc a0 a1 a2
3 82C50a pin description symbol pin number type active level description distr, distr 22 21 i i h l data in strobe, data in strobe: distr, distr are read inputs which cause the 82C50a to output data to the data bus (d0-d7). the data output depends upon the register selected by the address inputs a0, a1, a2. the chip select inputs cs0, cs1, cs2 enable the distr, distr inputs. only an active distr or distr , not both, is used to receive data from the 82C50a during a read operation. if distr is used as the read input, dlstr should be tied high. if distr is used as the active read input, distr should be tied low. dostr, dostr 19 18 i i h l data out strobe, data out strobe: dostr, dostr are write inputs which cause data from the data bus (d0-d7) to be input to the 82C50a. the data input depends upon the register selected by the address inputs a0, a1, a2. the chip select inputs cs0, cs1, cs2 enable the dostr, dostr inputs. only an active dostr or dostr , not both, is used to transmit data to the 82C50a during a write operation. if dostr is used as the write input, dostr should be tied high. if dostr is used as the write input, dostr should be tied low. d0-d7 1-8 i/o data bits 0-7: the data bus provides eight, three-state input/output lines for the transfer of data, control and status information between the 82C50a and the cpu. for character formats of less than 8 bits, d7, d6 and d5 are ?don?t cares? for data write operations and 0 for data read operations. t hese lines are normally in a high impedance state except during read operations. d0 is the least significant bit (lsb) and is the first serial data bit to be received or transmitted. a0, a1, a2 28, 27, 26 i i h register select: the address lines select the internal registers during cpu bus operations. see table 1. xtal1, xtal2 16 17 i o crystal/clock: crystal connections for the internal baud rate generator. xtal1 can also be used as an external clock i nput, in which case xtal2 should be left open. sout 11 o serial data output: serial data output from the 82C50a transmitter circuitry. a mark (1) is a logic one (high) and space (0) is a logic zero (low). sout is held in the mark condition when the transmitter is disabled, mr is true, the transmitter register is empty, or when in the loop mode. sout is not affected by the cts input. gnd 20 l ground: power supply ground connection (v ss ). cts 36 i l clear to send: the logical state of the cts pin is reflected in the cts bit of the (msr) modem status register (cts is bit 4 of the msr, written msr (4)). a change of state in the cts pin since the previous reading of the msr causes the setting of dcts (msr(o)) of the modem status register. when cts pin is active (low), the modem is indicating that data on sout can be transmi tted on the communications link. if cts pin goes inactive (high), the 82C50a should not be allowed to transmit data out of sout. cts pin does not affect loop mode operation. dsr 37 i l data set ready: the logical state of the dsr pin is reflected in msr(5) of the modem status register. ddsr (msr(1)) indicates whether the dsr pin has changed state since the previous reading of the msr. when the dsr pin is active (low), the modem is indicating that it is ready to exchange data with the 82C50a, while the dsr pin inactive (high) indicates that the m odem is not ready for data exchange. the active condition indicates only the condition of the local data communications equipment (dce), and does not imply that a data circuit as been established with remote equipment. dtr 33 o l data terminal ready: the dtr pin can be set (low) by writing a logic 1 to mcr(0), modem control register bit 0. this signal is cleared (high) by writing a logic 0 to the dtr bit (mcr(0)) or whenever a mr active (high) is applied to the 82C50a. when active (low), dtr pin indicates to the dce that the 82C50a is ready to receive data. in some instances, dtr pin is used as a power on indicator. the inactive (high) state causes the dce to disconnect the modem fr om the telecommunications circuit. rts 32 o l request to send: the rts signal is an output used to enable the modem. the rts pin is set low by writing a logic 1 to mcr (1) bit 1 of the modem control register. the rts pin is reset high by master reset. when active, the rts pin indicates to the dce that the 82C50a has data ready to transmit. in half duplex operations, rts is used to control the direction of the line. baudout 15 o baudout: this output is a 16x clock out used for the transmitter section (16x = 16 times the data rate). the baudout clock rate is equal to the reference oscillator frequency divided by the specified divisor in the baud rate generator divisor latches dll and dlm. baudout may be used by the receiver section by tying this output to rclk.
4 82C50a out1 34 o l output 1: this is a general purpose out put that can be programmed active (low) by settingvcr(2) (out1) of the modem control register to a high level. the out1 pin is set high by master reset. the out1 pin is inactive (high) during loop mode operation. out2 31 o l output 2: this is a general purpose out put that can be programmed active (low) by setting mcr(3) (out1) of the modem control register to a high level. the out2 pin is set high by master reset. the out2 signal is inactive (high) during loop mode operation. ri 39 1 l ring indicator: when low, ri indicates that a telephone ringing signal has been received by the modem or data set. the ri signal is a modem control input whose condition is tested by reading msr(6) (ri). the modem status register output teri (msr(2)) indicates whether the ri input has changed from a low to high since the previous reading of the msr. if the interrupt is enabled (ier (3) = 1) and ri changes from a low to high, an interrupt is generated. the active (low) state of ri indicates that the dce is receiving a ringing signal. ri will appear active for approximately the same length of time as the active segment of the ringing cycle. the inactive state of ri will occur during the inactive segments not detected by the dce. this circuit is not disabled by the inactive condition of dtr . dcd 38 i l data carrier detect: when active (low), dcd indicates that the data carrier has been detected by the modem or data set. dcd is a modem input whose condition can be tested by the cpu by reading msr(7) (dcd) of the modem status register. msr(3) (ddcd) of the modem status register indicates whether the dcd input has changed since the previous reading of the msr. dod has no effect on the receiver. if the dcd changes state with the modem status interrupt enabled, an interrupt is generated. when dcd is active (low), the received line signal from the remote terminal is within the limits specified by the dce manufacturer . the inactive (high) signal indicates that the signal is not within the spec ified limits, or is not present. mr 35 1 h master reset: the mr input forces the 82c 50a into an idle mode in which all serial data activities are suspended. the modem control register (mcr) along with its associated outputs are cleared. the line status register (lsr) is cleared except for the thre and temt bits, which are set. the 82C50a remains in an idle state until programmed to resume serial data activities. the mr input is a schmitt trigger input. see the dc electrical characterist ics for schmitt trigger logic input voltage levels. see table 7 for a summary of master reset?s effect on 82C50a operation. lntrpt 30 o h interrupt request: the lntrpt output goes active (high) when one of the following interrupts has an active (high) c ondition and is enabled by the interrupt enable register: receiver error flag, re ceived data available, transmitter holding register empty, and modem status. the lntrpt is reset low upon appropriate service or a mr operation. see figure 1. interrupt control structure. sin 10 i h serial data input: the sin input is the serial data input from the communication line or modem to the 82C50a receiver circuits . a mark (1) is high, and a space (0) is low. data inputs on sin are disabled when operating in the loop mode. v cc 40 h v cc : +5v positive power supply pin. a 0.1 a decoupling capacitor from v cc (pin 40) to gnd (pin 20) is recommended. cs0, cs1, cs2 12,13, 14 i i h, h, l chip select: the chip select inputs act as enable signals for the write (dostr, dostr ) and read (dlstr, dlstr ) input signals. the chip select inputs are latched by the ads input. nc 29 do not connect csout 24 o h chip select out: when active (high), this pin indicates that the chip has been selected by active cs0, cs1, and cs2 inputs. no data transfer can be initiated until csout is a logic 1, active (high). ddis 23 o h driver disable: this output is inactive (low) when the cpu is reading data from the 82C50a. an active (high) dells out put can be used to disable an external transceiver when the cpu is reading data. ads 25 i l address strobe: when active (low), ads latches the register select (a0, a1, a2) and chip select (cs0, cs1, cs2 ) inputs. an active ads is required when the register select pins are not stable for the duration of the read or write operation, multiplexed mode. if not required, the ads input should be tied low, non-multiplexed mode. rclk 9 i this input is the 16x baud rate clock for the receiver section of the 82C50a. this input may be provided from the baudout output or an external clock. pin description (continued) symbol pin number type active level description
5 82C50a block diagram distr distr dostr dostr ddis csout xtal1 xtal2 (22) (21) (19) (18) (23) (24) (16) (17) a0 a1 a2 cs0 cs1 cs2 ads mr (28) (27) (26) (12) (13) (14) (25) (35) d7 - d0 (1 - 8) (40) (20) data bus receiver shift buffer power supply select & control logic (10) sin (9) rclk (15) baudout (11) sout (32) rts (33) dtr (34) out1 (36) out2 (31) cts (37) dsr (38) dcd (39) ri receiver receiver timing & control transmitter timing & control transmitter shift register modem control logic receiver buffer register line control register baud rate generator divisor latch (ls) divisor latch (ms) line status register transmitter holding register modem control register modem status register interrupt enable register interrupt io register scratch register interrupt control logic (30) intrpt +5v gnd
6 82C50a accessible registers the three types of internal registers in the 82C50a used in the operation of the device are control, status, and data registers. the control regist ers are the bit rate select register dll and dlm, line control register, interrupt enable register and the modem control registers, while the status registers are the line status registers and the modem status register. the data registers are the receiver buffer register and transmitter holding register. the address, read, and write inputs are used in conjunction with the divisor latch access bit in the line control register (lcr(7)) to select the register to be written or read (see table 1.). individual bits within these registers are referred to by the register mnemonic and th e bit number in parenthesis. an example, lcr(7) refers to line control register bit 7. the transmitter buffer register and receiver buffer register are data registers holding from 5-8 data bits. if less than eight data bits are transmitt ed, data is right justified to the lsb. bit 0 of a data word is always the first serial data bit received and transmitted. the 82C50a data registers are double buffered so that read and write operations can be performed at the same time the uart is performing the parallel to serial and serial to parallel conversion. this provides the microprocessor with increased flexibility in its read and write timing. table 1. accessing 82C50a internal registers dlab a2 a1 a0 mnemonic register 0 0 0 0 rbr receiver buffer register (read only) 0 000 thr transmitter holding register (write only) 0 0 0 1 ler interrupt enable register x 0 1 0 iir interrupt identification register (read only) x 0 1 1 lcr line control register x 1 0 0 mcr modem control register x 1 0 1 lsr line status register x 1 1 0 msr modem status register x 1 1 1 scr scratch register 1 0 0 0 dll divisor latch (lsb) 1 0 0 1 dlm divisor latch (msb) note: x = ?don?t care?, 0 = logic low, 1 = logic high line control register (lcr) lcr 7 lcr 6 lcr 5 lcr 4 lcr 3 lcr 2 lcr 1 lcr 0 word length select 0 0 = 5 data bits 0 1 = 6 data bits 1 0 = 7 data bits 1 1 = 8 data bits stop bit select 0 = 1 stop bit 1 = 1.5 stop bits if 5 data bit word length is selected 2 stop bits if 6, 7, or 8 data bit word length is selected parity enable 0 = parity disabled 1 = parity enabled (generated & checked) even parity select 0 = odd parity when parity is enabled 1 = even parity when parity is enabled stick parity 0 = stick parity disabled 1 = when parity is enabled forces the transmission and checking of a parity bit of a known state. parity bit forced to a logic 1 if lcr (4) = 0 or to a logic 0 if lcr (4) = 1. break control 0 = break disabled 1 = break enabled. the serial output (sout) is forced to the spacing (logic 0) state. divisor latch access bit 0 = must be low to access the receiver buffer. transmitter holding register or the interrupt enable register. 1 = must be high to access the divisor latches dll and dlm of the baud rate generator during a read or write operation.
7 82C50a line control register (lcr) the format of the data character is controlled by the line control register. the contents of the lcr may be read, eliminating the need for separate storage of the line characteristics in system memo ry. the content s of the lcr are described below. lcr bits 0 thru 7 lcr (0) word length select bit 0 (wls0) lcr (1) word length select bit 1 (wls1) lcr (2) stop bit select (stb) lcr (3) parity enable (pen) lcr (4) even parity select (eps) lcr (5) stick parity lcr (6) set break lcr (7) divisor latch access bit (dlab) lcr(0) and lcr(1) word length select bit 0, word length select bit 1: the number of bits in each transmitted or received serial character is programmed as follows: lcr(2) stop bit select: lcr(2) specifies the number of stop bits in each transmitted char acter. if lcr(2) is a logic 0, one stop bit is generated in the transmitted data. if lcr(2) is a logic 1 when a 5-bit word lengt h is selected, 1.5 stop bits are generated. if lcr(2) is a l ogic 1 when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated. the receiver checks for two stop bits if programmed. lcr(3) parity enable: when lcr(3) is high, a parity bit between the last data word bi t and stop bit is generated and checked. lcr(4) even parity select: when parity is enabled (lcr(3) = 1), lcr(4) = 0 selects odd parity, and lcr(4) = 1 selects even parity. lcr(5) stick parity: when parity is enabled (lcr(3) = 1), lcr(5) = 1 causes the transmission and reception of a parity bit to be in the opposite state from that indicated by lcr(4). this allows the user to force parity to a known state and for the receiver to check the parity bit in a known state. lcr(6) break control: when lcr(6) is set to logic-1, the serial output (sout) is forced to the spacing (logic 0) state. the break is disabled by setting lcr(6) to a logic-0. the break control bit acts only on sout and has no effect on the transmitter logic. break control enables the cpu to alert a terminal in a computer communications system. if the following sequence is used, no erroneous or extraneous characters will be transmi tted because of the break. 1. load an all os pad character in response to thre. 2. set break in response to the next thre. 3. wait for the transmitter to be idle, (temt = 1), and clear break when normal transmission has to be restored. during the break, the transmitter can be used as a character timer to accurately establish the break duration. lcr(7) divisor latch access bit (dlab): lcr(7) must be set high (logic 1) to access the divisor latches dll and dlm of the baud rate gener ator during a read or write operation. lcr(7) must be input low to access the receiver buffer, the transmitter holdin g register, or the interrupt enable register. line status register (lsr) the lsr is a single register th at provides stat us indications. the lsr is usually the first re gister read by the cpu to determine the cause of an interrupt or to poll the status of the 82C50a. three error flags oe, fe, and pe provide the status of any error conditions detected in th e receiver circuitry. during reception of the stop bits, the error flags are set high by an error condition. the error flags are not reset by the absence of an error condition in the next received character. the flags reflect the last character only if no overrun occurred. the overrun error (oe) indicates that a character in the receiver buffer register has been overwritten by a character from the receiver shift register before being read by the cpu. the character is lost. framing error (fe) indicates that the last character received contained incorrect (low) stop bits. this is caused by the absence of the required stop bit or by a stop bit too short to be detected. pari ty error (pe) indicates that the last character received contained a parity error based on the programmed and calculat ed parity of the received character. the break interrupt (bi) status bit indicates that the last character received was a break character. a break character is an invalid data character, with the entire character, including parity and stop bits, logic zero. the transmitter holding register empty (thre) bit indicates that the thr register is empty and ready to receive another character. the transmission shift register empty (temt) bit indicates that the transmitter shift register is empty, and the 82C50a has completed transmission of the last character. if the interrupt is enabled (ler(1)), an active thre causes an interrupt (intrpt). the data ready (dr) bit indicates that the rbr has been loaded with a received character (including break) and that the cpu may access this data. reading the lsr clears lsr (1) - lsr (4). (oe, pe, fe and bi). lcr(1) lcr(0) word length 00 5 bits 01 6 bits 10 7 bits 11 8 bits
8 82C50a the contents of the line status register are indicated in the above table and are described below. lsr(0) data ready (dr): data ready is set high when an incoming character has been received and transferred into the receiver buffer register. lsr(0) is reset low by a cpu read of the data in the re ceiver buffer register. lsr(1) overrun error (oe): overrun error indicates that data in the receiver buffer re gister was not read by the cpu before the next character was transferred into the receiver buffer register, overwriting the previous character. the oe indicator is reset whenever the cpu reads the contents of the line status register. lsr(2) parity error (pe): parity error indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit (lcr (4)). the pe bit is set high upon detection of a parity error, and is reset low when the cpu reads the contents of the lsr. lsr(3) framing error (fe): framing error indicates that the received character did not have a valid stop bit. lsr(3) is set high when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). the fe indicator is reset low when t he cpu reads the contents of the lsr. lsr(4) break interrupt (bi): break interrupt is set high when the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). the b indicator is reset when the cpu reads the contents of the line status register. lsr(1) - lsr(4) are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the interrupt identification register (iir)) when any of the conditions are detected. this interrupt is enabled by setting ler (2) = 1 in the interrupt enable register. lsr(5) transmitter holding register empty (thre): thre indicates that the 82C50a is ready to accept a new character for transmission. the thre bit is set high when a character is transferred from the transmitter holding register into the transmitter shift register. lsr(5) is reset low by the loading of the transmitter holding register by the cpu. lsr(5) is not reset by a cpu read of the lsr. when the thre interrupt is enabled (ier(1) = 1), thre causes a priority 3 interrupt in t he lir. if thre is the interrupt source indicated in iir, lntrpt is cleared by a read of the iir. lsr(6) transmitter empty (temt): temt is set high when the transmitter holding register (thr) and the transmitter shift register (tsr ) are both empty. lsr(6) is reset low when a character is loaded into the thr and remains low until the character is transferred out of sout. temt is not reset low by a cpu read of the lsr. lsr(7): this bit is permanently set to logic 0. modem control register (mcr) the mcr controls the interface with the modem or data set as described below. the mcr can be written and read. the rts , dtr , out1 and out2 outputs are directly controlled by their control bits in this register. a high input asserts a low (true) at the output pins. mcr(0): when mcr(0) is set high, the dtr output is forced low. when mcr(0) is reset low, the dtr output is forced high. the dtr output of the 82C50a may be input into an ela inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. mcr(1): when mcr(1) is set high, the rts output is forced low. when mcr(1) is reset low, the rts output is forced high. the rts output of the 82C50a may be input into an ela inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. mcr(2): when mcr(2) is set high, the out1 output is forced low. when mcr(2) is reset low, the out1 output is forced high. out1 is an user designated output. lsr bits 0 thru 7 logic 1 logic 0 lsr (0) data ready (dr) ready not ready lsr (1) overrun error (oe) error no error lsr (2) parity error (pe) error no error lsr (3) framing error (fe) error no error lsr (4) break interrupt (bi) break no break lsr (5) transmitter holding register empty (thre) empty not empty lsr (6) transmitter empty (temt) empty not empty lsr (7) not used mcr bits 0 thru 7 mcr bit logic 1 mcr bit logic 0 mcr (0) data terminal ready (dtr) dtr output low dtr output high mcr (1) request to send (rts) rts output low rts output high mcr (2) out1 out1 output low out1 output high mcr (3) out2 out2 output low out2 output high mcr (4) loop loop enabled loop disabled mcr (5) 0 mcr (6) 0 mcr (7) 0
9 82C50a mcr(3): when mcr(3) is set high, the out2 output is forced low. when mcr(3) is reset low, the out2 output is forced high. out2 is an user designated output. mcr(4): mcr(4) provides a local loopback feature for diagnostic testing of the 62c50a. when mcr(4) is set high, serial output (sout) is set to the marking (logic 1) state, and the receiver data inpu t serial input (sin) is disconnected. the outpu t of the transmitter shift register is looped back into the receiver sh ift register i nput. the four modem control inputs (cts , dsr , dc, and ri ) are disconnected. the four modem control outputs (dtr , rts , out1 and out2 ) are internally connected to the four modem control inputs. the modem control output pins are forced to their inactive state (high). in the diagnostic mode, data transmitted is immediately received. this allows the processor to verify the transmit and receive data paths of the 82C50a. in the diagnostic mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the mcr inst ead of the four modem control inputs. the interrupts are still controlled by the interrupt enable register. mcr(5) - mcr(7): these bits are permanently set to logic 0. modem status register (msr) the msr provides the cpu with status of the modem input lines from the modem or periph eral device. the msr allows the cpu to read the modem signal inputs by accessing the data bus interface of the 82C50a. in addition to the current status information, four bits of the msr indicate whether the modem inputs have changed si nce the last reading of the msr. the delta status bits are set high when a control input from the modem changes state, and reset low when the cpu reads the msr. the modem input lines are cts (pin 36), dsr (pin 37), ri (pin 39), and dcd (pin 38). msr(4) - msr(7) are status indications of these lines. the status indications follow the status of the input lines. if t he modem status interrupt in the interrupt enable register is enabled (ier(3)), a change of state in a modem input signals will be reflected by the modem status bits in the li r register, and an interrupt (lntrpt) is generated. the msr is a priority 4 interrupt. the contents of the modem status register are described below: note that the state (high or low) of the status bits are inverted versions of the actual input pins. msr(0) delta clear to send (dcts): dcts indicates that the cts input (pin-36) to the 82C50a has changed state since the last time it was read by the cpu. msr(1) delta data set ready (ddsr): ddsr indicates that the dsr input (pin-37) to the 62c50a has changed state since the last time it was read by the cpu. msr(2) trailing edge of ring indicator (teri): teri indicates that the ri input (pin-39) to the 82C50a has changed state from low to high since the last time it was read by the cpu. high to low transitions on ri do not activate teri. modem control register (mcr) mcr 7 mcr 6 mcr 5 mcr 4 mcr 3 mcr 2 mcr 1 mcr 0 data terminal ready 0 = dtr output high (inactive) 1 = dtr output low (active) request to send 0 = rts output high (inactive) 1 = rts output low (active) out 1 0 = out 1 output high (inactive) 1 = out 1 output low (active) out 2 0 = out 2 output high (inactive) 1 = out 2 output low (active) loop 0 = loop disabled 1 = loop enabled these bits are permanently set to a logic 0. msr bits 0 thru 7 msr bit mnemonic description msr (1) ddsr delta data set ready msr (2) teri trailing edge of ring indicator msr (0) dcts delta clear to send msr (3) ddcd delta data carrier detect msr (4) cts clear to send msr (5) dsr data set ready msr (6) ri ring indicator msr (7) dcd data carrier detect
10 82C50a msr(3) delta data carrier detect (ddcd): ddcd indicates that the dcd input (pin-36) to the 82C50a has changed state since the last ti me it was read by the cpu. msr(4) clear to send (cts): clear to send (cts) is the status of the cts input (pin-36) from the modem indicating to the 82C50a that the modem is ready to receive data from the 62c50a transmitter output (sout). if the 82C50a is in the loop mode (mcr(4)=1), msr(4) is equivalent to rts in the mcr. msr(5) data set ready (dsr): data set ready (dsr) is a status of the dsr input (pin-37) from the modem to the 82C50a which indicates that the modem is ready to provide received data to the 82C50a rece iver circuitry. if the 82C50a is in the loop mode (mcr(4) = 1), msr(5) is equivalent to dtr in the mcr. msr(6) ring indicator msr(6): indicates the status of the ri input (pin-39). if the 82C50a is in the loop mode (mcr(4) = 1), msr(6) is equivalent to out1 in the mcr. msr(7) data carrier detect (msr(7)): data carrier detect indicates the status of the data carrier detect (dcd ) input (pin-38). if the 82C50a is in the loop mode (mcr(4) = 1), msr(4) is equivalent to out2 of the mcr. the modem status inputs (ri, dcd, dsr and cts) reflect the modem input lines wit h any change of status. reading the msr register will clear the delta modem status indications but has no effe ct on the status bits. the status bits reflect the state of the input pins regardless of the mask control signals. if a dct s, ddsr, teri, or ddcd are true and a state change occurs during a read operation (dlstr, distr ), the state change is not indicated in the msr. if dcts, ddsr, teri, or ddcd are false and a state change occurs during a read ope ration, the state change is indicated after the read operation. for lsr and msr, the setting of status bits is inhibited during status register read (distr, dlstr ) operations. if a status condition is generated during a read (dlstr, distr ) operation, the status bit is not set until the trailing edge of the read (distr, distr ). if a status bit is set during a read (dlstr, distr ) operation, and the same status condition occurs, that status bit will be cleared at the trailing edge of the read (dlstr, distr ) instead of being set again. baud rate select register (brsr) the 82C50a contains a programmable baud rate generator (brg) that divides the clock (dc to 10mhz) by any divisor from 1 to 2 16 -1 (see also brg description). the output frequency of the baud g enerator is 16x the data rate [divisor # = frequency input (baud rate x 16)]. two 8-bit divisor latch registers store th e divisor in a 16-bit binary format. these divisor latch registers must be loaded during initialization. upon loading eit her of the divisor latches, a 16-bit baud counter is immedi ately loaded. this prevents long counts on initial load. sample divisor number calculation: given: desired baud rate 1200 baud frequency input 1.8432mhz formula: divisor # = frequency input (baud rate x 16) divisor # = 1843200 (1200 x 16) answer: divisor # = 96 = 60 hex dll = 01100000 dlm = 00000000 check: the divisor # 96 will divide the input frequency 1.8432mhz down to 19200 which is 16 times the desired baud rate. receiver buffer register (rbr) the receiver circuitry in the 82C50a is programmable for 5, 6, 7 or 8 data bits per character. for words of less than 8 bits, the data is right justified to the least significant bit (lsb = data bit 0 (rbr(0)). data bi t 0 of a data word (rbr(0)) is the first data bit received. the unused bits in a character less than 8 bits are output low to the parallel output by the 82C50a. received data at the sin input pin is shifted into the receiver shift register by the 16x clock provided at the rclk input. this clock is synchro nized to the incoming data based on the position of the st art bit. when a complete character is shifted into the receiver shift register, the assembled data bits are parallel loaded into the receiver buffer register. the dr flag in the lsr register is set. double buffering of the rece ived data permits continuous reception of data without losing received data. while the receiver shift register is shifting a new character into the 82C50a, the receiver buffer register is holding a previously received character for the cpu to read. failure to read the divisor latch least significant byte dll (0) bit 0 dll (1) bit 1 dll (2) bit 2 dll (3) bit 3 dll (4) bit 4 dll (5) bit 5 dll (6) bit 6 dll (7) bit 7 divisor latch most significant byte dlm (0) bit 8 dlm (1) bit 9 dlm (2) bit 10 dlm (3) bit 11 dlm (4) bit 12 dlm (5) bit 13 dlm (6) bit 14 dlm (7) bit 15
11 82C50a data in the rbr before comple te reception of the next character result in the loss of the data in the receiver register. the oe flag in the lsr register indicates the overrun condition. transmitter holding register (thr) the transmitter holding register (thr) holds parallel data from the data bus (d0-d7) un til the transmitter shift register is empty and ready to accept a new character for transmission. the transmitter and receiver word length and number of stop bits are the same. if the character is less than eight bits, unused bits at the microprocessor data bus are ignored by the transmitter. data bit 0 (thr(0)) is the first serial data bit transmitted. the thre flag (lsr(5)) reflect the status of the thr. the temt flag (lsr(6)) indicates if both the thr and tsr are empty. scratchpad register (scr) this 8-bit read/write register has no effect on the 82C50a. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. interrupt structure interrupt identification register (iir) the 82C50a has interrupt capability for interfacing to current microprocessors. in order to minimize software overhead during data character transfe rs, the 82C50a prioritizes interrupts into four levels. the four levels of interrupt conditions are as follows: 1. receiver line status (priority 1) 2. received data ready (priority 2) 3. transmitter holding register empty (priority 3) 4. modem status (priority 4). information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the interrupt identification r egister (iir). when addressed during chip select time, the lir indicates the highest priority interrupt pending. no other interrupts are acknowledged until the interrupt is serviced by the cp u. the contents of the lir are indicated in table 2 and are described below. iir(0): iir(0) can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. when iir(0) is low, an interrupt is pending, and the lir contents may be used as a pointer to the appropriate interrupt service routine. when lir(0) is high, no interrupt is pending. ilr(1) and iir(2): llr(1) and ilr(2) are used to identify the highest priority interrupt pending as indicated in table 2. lir(3) - iir(7): these five bits of the lir are logic 0. rbr bits 0 thru 7 rbr (0) data bit 0 rbr (1) data bit 1 rbr (2) data bit 2 rbr (3) data bit 3 rbr (4) data bit 4 rbr (5) data bit 5 rbr (6) data bit 6 rbr (7) data bit 7 thr bits 0 thru 7 thr (0) data bit 0 thr (1) data bit 1 thr (2) data bit 2 thr (3) data bit 3 thr (4) data bit 4 thr (5) data bit 5 thr (6) data bit 6 thr (7) data bit 7 scr bits 0 thru 7 scr (0) data bit 0 scr (1) data bit 1 scr (2) data bit 2 scr (3) data bit 3 sor (4) data bit 4 scr (5) data bit 5 sor (6) data bit 6 scr (7) data bit 7 table 2. interrupt iden tification register interrupt identification interrupt set and reset functions bit 2 bit 1 bit 0 priority level interrupt flag interrupt source interrupt reset control x x 1 none none 1 1 0 first receiver line status oe, pe, fe, or bi lsr read 1 0 0 second received data available r eceiver data available rbr read 0 1 0 third thre thre iir read if thre is the interrupt source or thr write 0 0 0 fourth modem status cts , dsr , ri , dcd msr read note: x = not defined, may be 0 or 1
12 interrupt enable register (ier) the interrupt enable register (ier) is a write register used to independently enable the four 82C50a interrupts which activate the interrupt (lntrpt) output. all interrupts are disabled by resetting ier(0) - ier(3) of the interrupt enable register. interrupts are enabled by setting the appropriate bits of the ier high. disabling the interrupt system inhibits the interrupt identification register and the active (high) intrpt output. all other system function s operate in their normal manner, including the setting of the line status and modem status registers. t he contents of the interrupt enable register are indicated in table 3 and are described below. ier(0): when programmed high (ier(0) = logic 1), ier(0) enables received data available interrupt. ier(1): when programmed high (ier(1) = logic 1), ier(1) enables the transmitter holding register empty interrupt. ier(2): when programmed high (ier(2) = logic 1), ier(2) enables the receiver li ne status interrupt. ier(3): when programmed high (ier(3) = logic 1), ier(3) enables the modem status interrupt. ier(4) - ier(7): these four bits of the ier are logic 0. figure 1. 82C50a interrupt control structure intrpt pin 30 dr (lsr bit 0) erbfi (ier bit 0) oe (lsr bit 1) pe (lsr bit 2) thre (lsr bit 5) etbei (ier bit 1) fe (lsr bit 3) bi (lsr bit 4) elsi (ier bit 2) dcts (msr bit 0) ddsr (msr bit 1) teri (msr bit 2) ddcd (msr bit 3) edssi (ier bit 3) table 3. 82C50a accessi ble register summary (note: see table 1 for how to access these registers.) register mnemonic register bit number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rbr (read only) data bit 7 (msb) data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 (lsb) ? thr (write only) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 dll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dlm bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ier0000(edssi) enable modem status interrupt (elsi) enable receiver line status interrupt (etbei) enable transmitter holding register empty interrupt (erbfi) enable received data available interrupt iir (read only) 0 0 0 0 0 interrupt id bit (1) interrupt id bit (0) ?0? 1f interrupt pending lcr (dlab) divisor latch access bit set break stick parity (eps) even parity select (pen) parity enable (stb) number of stop bits (wlsb1) word length select bit 1 (wlsb0) word length select bit 0 mcr 0 0 0 loop out 2 out 1 (rts) request to send (dtr) data terminal ready lsr 0 (temt) transmitter empty (thre) transmitter holding register empty (bi) break interrupt (fe) framing error (pe) parity error (oe) overrun error (dr) data ready msr (dcd) data carrier detect (ri) ring indicator (dsr) data set ready (cts) clear to send (ddcd) delta data carrier detect (teri) trailing edge ring indicator (ddsr) delta data set ready (dcts) delta clear to send scr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? lsb, data bit 0 is the firs t bit transmitted or received. 82C50a
13 82C50a transmitter the serial transmitter section consists of a transmitter holding register (thr), transmitter shift register (tsr), and associated control logic. the transmitter holding register empty (thre) and transmitter shift register empty (temt) are two bits in t he line status register which indicate the status of thr and tsr. to transmit a 5-8 bit word, the word is written through d0-d7 to the thr. the microprocessor should perform a write operation only if thre is high. the thre is set high when the word is automatically transferred from the thr to the tsr during the transmission of the start bit. when the transmitter is idle, both thre and temt are high. the first word written causes thre to be reset to 0. after completion of the transfer, thre returns high. temt remains low for at least the duration of the transmission of the data word. if a second char acter is transmitted to the thr, the thre is reset low. since the data word cannot be transferred from the thr to th e tsr until the tsr is empty, thre remains low until the tsr has completed transmission of the word. when the last word has been transmitted out of the tsr, temt is set high. thre is set high one thr to tsr transfer time later. receiver serial asynchronous data is input into the sin pin. the idle state of the line providing the input into sin is high. a start bit detect circuit continually searches for a high to low transition from the idle state. when the transition is detected, a counter is reset, and counts the 16x clock to 7 1/2, which is the center of the start bi t. the start bit is va lid if the sin is still low at the mid bit sample of the start bit. verifying the start bit prevents the receiver from assembling an incorrect data character due to a low going noise spike on the sin input. the line control register determines the number of data bits in a character (lcr(0), l cr(1)), number of stop bits lcr(2), if parity is used l cr(3), and the polarity of parity lcr(4). status information for the receiver is provided in the line status register. when a c haracter is transferred from the receiver shift register to the receiver buffer register, the data received indication in lsr(0) is set high. the cpu reads the receiver buffer regi ster through d0-d7. this read resets lsr(0). if d0-d7 are not read prior to a new character transfer from the rsr to the rbr, the overrun error status indication is set in lsr(1). the parity check tests for even or odd parity on the parity bit, which precedes the first stop bit. if there is a parity error, the parity error is set in lsr (2). there is circuitry which tests whet her the stop bit is high. if it is not, a framing error indication is generated in lsr(3). the center of the start bit is def ined as clock count 7 1/2. if the data into sin is a symmetric al square wave, the center of the data cells will occur within 3.125% of the actual center, providing an error margin of 46.875%. the start bit can begin as much as one 16x clock cycle prior to being detected. baud rate generator (brg) the brg generates the clocking for the uart function, providing standard ansi/ccitt bit rates. the oscillator driving the brg may be provided either with the addition of an external crystal to the xtal1 and xtal2 inputs, or an external clock into xtal1. in either case, a buffered clock output, baudout , is provided for other system clocking. if two 82C50as are used on the same board, one can use a crystal, and the buffered clock output can be routed directly into the xtal1 of the second 82C50a. the data rate is determined by the divisor latch registers dll and dlm and the external frequency or crystal input, with the baudout providing an output 16x the data rate. the bit rate is selected by programming the two divisor latches, divisor latch most significant byte and divisor latch least significant byte. setting dll = 1 and dlm = 0 selects the divisor to divide by 1 (divide by 1 gives maximum baud rate for a given input frequency at xtal1). the on-chip oscillator is optimized for a 10mhz crystal. usually, higher frequency are less expensive than lower frequency crystals. the brg can use any of three different popular crystals to provide standard baud rates. the frequency of these three common crystals on the market are 1.8432mhz, 2.4576mhz, and 3.072mhz. with these standard crystals, standard bit rates from 50 to 38.5kbps are available. the following tables illustrate the divisors needed to obtain standard rates using these three crystal frequencies. table 4. baud rates using 1.8432mhz crystal desired baud rate divisor used to generate 16 x clock percent error difference between desired and actual 50 2304 - 75 1536 - 110 1047 0.026 134.5 857 0.058 150 768 - 300 384 - 600 192 - 1200 96 - 1800 64 - 2000 58 0.69 2400 48 - 3600 32 - 4800 24 - 7200 16 - 9600 12 - 19200 6 - 38400 3 - 56000 2 2.86
14 reset after powerup, the 82C50a master reset schmitt trigger input (mr) should be held high for tmrw ns to reset the 82C50a circuits to an idle mode until initialization. a high on mr causes the following: 1. initializes the transmitter and receiver internal clock counters. 2. clears the line status register (lsr), except for transmitter shift register empty (te mt) and transmit holding register empty (thre), which are set. the modem control register (mcr) is also cleared. all of the discrete lines, memory elements and miscellaneous logic associated with these register bits are also cleared or turned off. divisor latches, receiver buffer register, transmitter buffer regi ster are not effected. following removal of the reset condition (mr low), the 82C50a remains in the idle mode until programmed. a hardware reset of the 82C50a sets the thre and temt status bit in the lsr. when interrupts are subsequently enabled, an interrupt occurs due to thre. a summary of the effect of a master reset on the 82C50a is given in table 7. table 5. baud rates using 2.4576mhz crystal desired baud rate divisor used to generate 16 x clock percent error difference between desired and actual 50 3072 - 75 2048 - 110 1396 0.026 134.5 1142 0.0007 150 1024 - 300 512 - 600 256 - 1200 128 - 1800 85 0.392 2000 77 0.260 2400 64 - 3600 43 0.775 4800 32 - 7200 21 1.587 9600 16 - 19200 8 - 38400 4 - table 6. baud rates using 3.072mhz crystal desired baud rate divisor used to generate 16 x clock percent error difference between desired and actual 50 3840 - 75 2560 - 110 1745 0.026 134.5 1428 0.034 150 1280 - 300 640 - 600 320 - 1200 160 - 1800 107 0.312 2000 96 - 2400 80 - 3600 53 0.628 4800 40 - 7200 27 1.23 9600 20 - 19200 10 - 38400 5 - table 7. 82C50a reset operations register/signal reset control reset interrupt enable register master reset all bits low (0-3 forced and 4-7 permanent) interrupt identification register master reset bit 0 is high, bits 1 and 2 low bits 3-7 are permanently low line control register master reset all bits low modem control register master reset all bits low line status register master reset all bits low, except bits 5 and 6 are high modem status register master reset bit 0-3 low bits 4-7 input signal sout master reset high lntrpt (rcvr errs) read lsr/mr low lntrpt (rcvr data ready) read rbr/mr low lntrpt (thre) read lir/write thr/mr low lntrpt (modem status changes) read msr/mr low out2 master reset high rts master reset high dtr master reset high out1 master reset high 82C50a
15 82C50a programming the 82C50a is programmed by the control registers lcr, ler, dll and dlm, and mcr. these control words define the character length, number of stop bits, parity, baud rate, and modem interface. while the control registers can be written in any order, the ler should be written to last bec ause it controls the interrupt enables. once the 82C50a is programmed and operational, these registers can be updated any time the 82C50a is not transmitting or receiving data. the control signals required to access 82C50a internal registers are shown below. software reset a software reset of the 82C50a is a useful method for returning to a completely known state wit hout a system reset. such a reset consists of writing to the lcr, divisor latches, and mcr registers. the lsr and rbr registers should be read prior to enabling interrupts in order to clear out any residual data or status bits which may be invalid for subsequent operation. crystal operation the 82C50a crystal oscillator ci rcuitry is designed to operate with a fundamental mode, paralle l resonant crystal. table 8 shows the required crystal parameters and crystal circuit configuration, respectively. when using an external clock source, the xtal1 input is driven and the xtal2 output is left open. power consumption when using an external clock is typically 50% of that required when using a crystal. this is due to the sinusoidal nature of the drive circuitry when using a crystal. the maximum frequency of the 82C50a is 10mhz with an external clock or a crystal attached to xtal1 and xtal2. using the external clock or crystal, and a divide by one divisor, the maximum baudout is 10mhz, and the maximum data rate is 625kbps. table 8. typical crystal oscillator circuit parameter frequency 1.0 to 10mhz type of operation parallel resonant, fundamental mode load capacitance (cl) 20 or 32pf (typ) r series (max) 100 ? (f = 10mhz, cl = 32pf) 200 ? (f = 10mhz, cl = 20pf) figure 2. typical crystal oscillator circuit cl xtal xtal1 xtal2 to baud rate generator logic pin 17 pin 16 rs cl 82C50a
16 82C50a absolute maximum rati ngs thermal information supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.5v to v cc +0.5v operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range cx82C50a-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c ix82C50a-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) plastic dip package. . . . . . . . . . . . . . . 45 n/a plastic lcc package . . . . . . . . . . . . . . 50 n/a maximum junction temperature plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150 o c max storage temperature range . . . . . . . . . . . . . -65 o c to +150 o c max lead temperature (soldering 10s) . . . . . . . . . . . . . . . .+300 o c (lead tips only for surface mount packages) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1788 gates caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. dc electrical specifications v cc = 5.0v 10%, t a = 0 o c to +70 o c (cx82C50a-5) t a = -40 o c to +85 o c (lx82C50a-5) symbol parameter min max units test conditions v ih logical one input voltage 2.0 - v v il logical zero input voltage - 0.8 v vth schmitt trigger logic one input voltage 2.0 - v mr input vtl schmitt trigger logic zero input voltage - 0.8 v mr input vih (clk) logical one clock voltage v cc -0.8 - v external clock vll (clk) logical zero clock voltage - 0.8 v external clock v oh output high voltage 3.0 - v i oh = -2.5ma v cc -0.4 - v i oh = -100 a v ol output low voltage - 0.4 v l ol = +2.5ma, ii input leakage current -1.0 +1.0 av in = gnd or v cc , dip pins 9,10,12, 13, 14, 18, 19, 21, 22, 25-28, 35-39 io input/output leakage current -10.0 +10.0 av o = gnd or v cc , dip pins 1-8 iccop operating power supply current - 6 ma external clock f = 2.4576mhz, v cc = 5.5v, v in = v cc or gnd, outputs open iccsb standby supply current - 100 av cc = 5.5v, v in = v cc or gnd, outputs open capacitance t a = 25 o c symbol parameter typical units test conditions cin input capacitance 15 pf freq = 1mhz, all measurements are referenced to device gnd cout output capacitance 15 pf ci/o i/o capacitance 20 pf
17 82C50a ac electrical specifications v cc = 5.0v 10%, t a = 0 o c to +70 o c (cx82C50a-5) t a = -40 o c to +85 o c (lx82C50a-5) timing requirements symbol parameter 82C50a-5 test conditions min max units (1) taw address strobe width 50 - ns (2) tas address setup time 60 - ns note 1 (3) tah address hold time 0 - ns (4) tcs chip select setup time 60 - ns note 1 (5) tch chip select hold time 0 - ns (6) tdiw distr dlstr strobe width 150 - ns (7) trc read cycle delay 270 - ns note 1 (8) rc read cycle = tar + tdiw + trc 500 - ns (9) tdd distr dlstr to driver disable delay - 75 ns (10) tddd delay from distr dlstr to data - 120 ns (11) thz dlstr distr to floating data delay 10 75 ns (12) tdow dostr dostr strobe width 150 - ns (13) twc write cycle delay 270 - ns note 1 (14) wc write cycle = taw + tdow + twc 500 - ns (15) tds data setup time 90 - ns (16) tdh data hold time 60 - ns note: 1. ?when using the 82C50a in the multiplexed mode (ads operational), it will operate in 80c86/ 88 systems with a maximum 3mhz operating frequency.? ac electrical specifications v cc = 5.0v 10%, t a = 0 o c to +70 o c (cx82C50a-5) t a = -40 o c to +85 o c (lx82C50a-5) timing symbol parameter 82C50a-5 units test conditions min max demultiplexed operation (17) tcsc chip select output delay from select - 125 ns (18) tra address hold time from distr distr 20 - ns (19) trcs chip select hold time from distr distr 20 - ns (20) tar distr distr delay from address 80 - ns (21) tcsr distr distr delay from chip select 80 - ns (22) twa address hold time from dostr dostr 20 - ns (23) twcs chip select hold time from dostr dostr 20 - ns (24) taw dostr dostr delay from address 80 - ns (25) tcsw dostr dostr delay from select 80 - ns (26) tmrw master reset pulse width 500 - ns (27) txh duration of clock high pulse 40 - ns (28) txl duration of clock low pulse 40 ns
18 82C50a baud generator (29) n baud divisor 1 2 16 -1 (30) tbld baud output negative edge delay - 250 ns (31) tbhd baud output positive edge delay - 250 ns (32) tlw baud output down time 40 - ns t xl = 50ns (33) thw baud output up time 40 - ns t xh = 50ns receiver (34) tscd delay from rclk to sample time - 250 ns (35) tslnt delay from stop to set interrupt 1 1 baudout cycles (36) trlnt delay from distr distr (rd rbr) to reset interrupt - 250 ns transmitter (37) thr delay from dostr dostr to reset interrupt - 250 ns (38) tlrs delay from initial intr reset to transmit start 8 24 baudout cycles (39) ts1 delay from initial write to interrupt 16 32 baudout cycles (40) tstl delay from stop to interrupt (thre) 8 24 baudout cycles (41) tir delay from distr distr (rd lir) to reset interrupt (thre) - 250 ns modem control (42) tmdo delay from dostr dostr to output - 500 ns (43) tsim delay to set interrupt from modem input - 500 ns (44) trim delay to reset interrupt from distr dlstr (rd msr) - 500 ns ac electrical specifications v cc = 5.0v 10%, t a = 0 o c to +70 o c (cx82C50a-5) t a = -40 o c to +85 o c (lx82C50a-5) timing (continued) symbol parameter 82C50a-5 units test conditions min max
19 82C50a ac test circuit ac testing input, output waveform test condition definition table ioh iol v1 r1 c1 -2.5ma +2.5ma 1.7v 520 ? 100pf output from device under test test c1 (note) point note: includes stay and jig capacitance. v1 r1 input v ih + 0.4v v il - 0.4v output v oh v ol 1.5v 1.5v ac testing: all input signals must switch between v il -0.4v and v ih +0.4v. input rise and fall times are driven at 1ns/v. timing waveforms figure 3. external clock input figure 4. ac test points figure 5. baudout timing 2.0v 0.8v txh (27) xtal1 txl (28) 2.0v 2.0v 0.8v 0.8v n (29) xtal1 (31) tbhd (30) tbld thw (33) tlw (32) tlw (32) tlw (32) thw (33) (30) tbld (30) tbld (31) tbhd (31) tbhd (30) tbld tlw = 2xtal1 cycles (32) thw = (n - 2) xtal1 cycles (33) (31) tbhd thw (33) baud out ( 1) baud out ( 2) baud out ( 3) baud out ( n, n > 3) note: tbld ( 1) is the only spec measure from xt l1 falling edge. all other tbld?s and tbhd?s are measured from xtal1 rising edge.
20 82C50a figure 6. write cycle figure 7. read cycle timing waveforms (continued) (1) taw (2) tas (3) tah (4) tcs (5) tch valid valid (17) tcsc ? (25) tcsw ? (24) taw ? (12) tdow (13) twc (14) wc or active active valid data (15) tds (16) tdh active (23) twcs ? (22) twa ? dostr /dostr distr /distr data d0-d7 csout cs 2, cs1, cs0 a2, a1, a0 ads ? applicable only when ads is tied low. (1) taw (2) tas (3) tah (4) tcs (5) tch valid valid (17) tcsc ? (21) tcsr ? (20) tar ? (6) tdiw (7) trc (8) rc or active active valid data tddd (11) thz active (19) trcs ? (18) tra ? distr /distr dostr /dostr data d0-d7 csout cs 2, cs1, cs0 a2, a1, a0 ads ? applicable only when ads is tied low. dd/s (10) tdd (9) tdd (9)
21 82C50a figure 8. receiver timing figure 9. transmitter timing timing waveforms (continued) tscd (34) 8 clks rclk sample clk sin (receiver input data) sample clk interrupt (data ready or rcvr err) distr /distr (read rec data buffer or rolsr) note 2 start data bits (5-8) parity stop tsint (35) trint (36) active notes: 1. see write cycle timing. 2. see read cycle timing. notes: 1. see write cycle timing. 2. see read cycle timing. start data (5-8) parity stop (1-2) start tsti (40) tir (41) serial out (sout) interrupt (thre) dostr /dostr (wr thr) note 1 distr /distr (rd iir) note 2 (38) tirs (39) tsi (37) thr (37) thr
22 82C50a figure 10. modem controls timing timing waveforms (continued) active active tmdo (42) tmdo (42) trim (44) (43) tsim tsim (43) tsim (43) dostr /dostr (wr mcr) note 1 rts , dtr out1 , out2 cts , dst , dcd interrupt distr /distr (rd msr) note 2 ri active trim (44) notes: 1. see write cycle timing. 2. see read cycle timing.
23 82C50a dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e40.6 (jedec ms-011-ac issue b) 40 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.980 2.095 50.3 53.2 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n40 409 rev. 0 12/93
24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com 82C50a plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l n44.65 (jedec ms-018ac issue a) 44 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.685 0.695 17.40 17.65 - d1 0.650 0.656 16.51 16.66 3 d2 0.291 0.319 7.40 8.10 4, 5 e 0.685 0.695 17.40 17.65 - e1 0.650 0.656 16.51 16.66 3 e2 0.291 0.319 7.40 8.10 4, 5 n44 446 rev. 2 11/97

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